Summary, copied from pages 131,132 of the thesis book.
For more information, or a hardcopy version (ISBN: 90-74795-58-7) please contact me at theodosis@papathanasiadis.gr

 

Image Compression Hardware

PhD Thesis by Theodossis Papathanassiadis

Images occupy a large amount of digital space in their conventional pixel representation format. Image compression techniques can exploit the high degree of data redundancy in pixel representations and result in significant reduction of the image size, thus relaxing the storage and communication capacity requirements of computer systems and digital networks.

The development of compression technology for images and other types of data, such as text, binary document images, sound, image sequences, has played an important role in today's multimedia revolution. The definition of a series of compression standards has opened up the way for widespread compression use in applications involving data storage and communication.

The JPEG image compression standard has been defined by an international joint ISO/CCITT committee. It can achieve compression ratios ranging from 1:1.5 up to 1:5 for lossless compression where the image pixel values can be reconstructed with their exact original values, and from 1:5 up to 1:100 for lossy compression where a degree of pixel value variation and image quality degradation is accepted.

During the standard's development period, in the late 80s, it was felt that the computing power required for compression processing is significant. Experiments showed that a typical high-end personal computer of the time could achieve compression processing pixel rates in the order of 0.015 - 0.025 Mbytes/sec. In practical terms, the user needed to wait for almost a minute before a 1.2 Mbyte image, a typical screen-full picture, could be recalled from storage, decompressed and viewed on the screen.

The work of the author in the period from 1988 up to 1991 concentrated on the design and implementation of low-cost image compression processing add-on boards, to accelerate compression performance of personal computer systems in a cost effective way.

During the design study, the properties, processing and storage requirements of the JPEG image compression algorithm have been analysed. It has been concluded that the most intensive part of the algorithm involved a large amount of multiply-add operations, while the actual memory size requirement for temporary data storage during processing was low, in the order of a few Kbytes. These characteristics matched perfectly with the properties of low-cost Digital Signal Processing components, such as the DSP16A processor from AT&T. The detailed architectural design and implementation work resulted in the PCodec, which has been used as an add-on board for image compression and decompression operations in IBM-compatible personal computer systems. Its cost was only a fraction of the total computer system, while it accelerated JPEG operations by a factor of 30, when compared to the main system processor, achieving a pixel throughput rate of 0.4 Mbytes/sec. At its time, the PCodec board demonstrated the advantages of compression techniques without the burden of the personal computer slow processing time.

The second generation image compression accelerator board, the MaCodec, has enhanced the capabilities of PCodec in three directions, (i) the reduction of overall cost by optimisation of the hardware components used, (ii) the enhancement of the processing power by introducing a twin- processor parallel implementation and (iii) the integration of the board into the Apple Macintosh operating system and image processing/editing application for user friendly operation. The MaCodec board achieved a pixel throughput rate of 0.7 Mbytes/sec, a speed-up factor of about 30 compared to a Macintosh of the time, and opened up the way to extensive image compression use in image applications such as desktop publishing.

In the period from 1991 to 1994, the Image Block Partitioning, IBP, scheme has been defined, evaluated and implemented by the author, as an attempt to improve the properties and enhance the applicability of image compression techniques. IBP involves the partitioning of the image into small blocks, typically of 16x16 or 32x32 pixel size. The blocks are compressed independently from each other, and are stored into the compressed data stream together with suitable pointers for independent retrieval. IBP opens up new possibilities for efficient selective pixel block extraction from compressed data, and parallel processing image compression and decompression implementations. It has been shown through practical experiments that the IBP scheme results in a small degradation of compression ratios, typically between 1% and 20%, which can be tolerated for most applications. An IBP based lossless image compression engine has been implemented in full-custom VLSI technology, demonstrating the capability of the scheme to integrate successfully into personal computer systems, leading into transparent use of compressed image data in the internal working memory system resources.

The work presented in this thesis has focused on several hardware implementation issues of image compression techniques. A significant amount of knowledge has been acquired on the question of hardware / software interaction, application integration, optimal processing structures for compression algorithms, the organisation and format of compressed data, and last but not least, detailed hardware design of VLSI image compression engines. Due to the explosive character of technological progress in the fields of computer multimedia technology, the performance achievements of this work may look obsolete in today's standards, however, the acquired know-how and experience has already contributed, and will hopefully continue to contribute in the future in the understanding of hardware architecture design issues for specialised applications.

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